
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY vga_test IS
END vga_test;
 
ARCHITECTURE behavior OF vga_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT vga
    PORT(
         clk25 : IN  std_logic;
			reset : IN std_logic;
			red_in : in std_logic;
         red_out : OUT  std_logic;
         green_out : OUT  std_logic;
         blue_out : OUT  std_logic;
         hs_out : OUT  std_logic;
         vs_out : OUT  std_logic);
    END COMPONENT;
    

   --Inputs
   signal clk25 : std_logic := '0';
	signal reset : std_logic := '0';
	signal red_in : std_logic := '0';

 	--Outputs
   signal red_out : std_logic;
   signal green_out : std_logic;
   signal blue_out : std_logic;
   signal hs_out : std_logic;
   signal vs_out : std_logic;

   -- Clock period definitions
   constant clk25_period : time := 80 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: vga PORT MAP (
          clk25 => clk25,
			 reset => reset,
			 red_in =>red_in,
          red_out => red_out,
          green_out => green_out,
          blue_out => blue_out,
          hs_out => hs_out,
          vs_out => vs_out
        );

   -- Clock process definitions
   clk25_process :process
   begin
		clk25 <= '0';
		wait for clk25_period / 2;
		clk25 <= '1';
		wait for clk25_period / 2;
   end process;
	
	stimulus_process :process
   begin
		reset <= '1';
		red_in <= '1';
		wait for clk25_period * 10;
		reset <= '0';
		wait;
   end process;


END;
